I'm in the process of evaluating a design migration from Xilinx(AMD) FPGAs to Intel FPGAs. However, some of our design uses Xilinx Parameterized Macros listed in this Xilinx Guide. I am wondering if Quartus has any sort of macro library for SystemVerilog and VHDL designs? Most of the macros we use are pretty basic and are just pulse synchronizers, bus synchronizers, FIFOs, AXI-S FIFOs, and RAM related.
If you're looking for template, can go to Insert Template icon after creating new file see the image below.
Can also go to File -> Create / Update to convert current file to other file format for example: bdf file to VHDL file (Pro don't have this).
If for IP or Qsys, the instantiation file will be generated automatically after HDL generation. Each IP has its specific document respectively.
Design Recommendations documents probably can help you as well check the links below: https://www.intel.com/content/www/us/en/docs/programmable/683082/22-2/recommended-hdl-coding-styles.html (Pro) https://www.intel.com/content/www/us/en/docs/programmable/683323/18-1/recommended-design-practices.html (Standard/Lite)
You can find more resources in Intel website https://www.intel.com/content/www/us/en/homepage.html. Let me know if I miss anything.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.