I have an AXI component that only needs to read so it does not implement the AXI write channels. Using the component editor in Qsys this gives errors.Any way around this? I guess I can create dummy AXI Write channel signals and tie off the outputs and not connect the inputs.
--- Quote Start --- What kind of errors? --- Quote End --- Hello Steve, Qsys says it is missing the address write and write data channels. It's perfectly legal to create an AXI component that just writes or just reads. So this should not be an error. I added the address write and write signals and tied off the outputs driving the rest of the AXI interconnect. Cheers, Tom