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5741 Discussions

About altera_a10_xcvr_clock_module, CLKUSR pin of Arria 10

lambert_yu
Beginner
384 Views

Hi sir/medam,

   I have one question about CLKUSR pin,

   1) From the Arria 10 transceiver PHY UG, it said that if there's transceiver channels in project, it must provide one stable and about 100~125Mhz clk to CLKUSR pin for transceiver calibration. I think that if we want to use transceiver, we must use CLKUSR pin.

   2) From the UG, It said that "If you are using the CLKUSR pin for your own logic (feeding it to the core), you must instantiate altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));" ? What does this sentence mean?

     a. It means that if I want use the clock from CLKUSR pin as the clock of core, we must instance above module to import the clock into the fpga core to use as user mode clock?  If so, I think clk_in port is one output port, but from my synthesize result, I find that's wrong. 

     b. Or it have other means?

  Could someone help me about this problem?

Brs,

Lambert

0 Kudos
1 Solution
Deshi_Intel
Moderator
341 Views

Hi Lambert,


I can sense your confusion.


You are still trying to touch on "mgmt_clk".

  • You don't need to do any extra connection to mgmt_clk.
  • When you instantiate "altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk))". It basically tell Quartus to do some internal background processing. User is not suppose to use or connect mgmt_clk to any signal (including clkusr)


Let me explain again.


(A) If you plan to use transceiver, provide on board external clock to FPGA clkusr pin

  • DO NOT connect clkusr port to anything in your RTL design anymore


(B) If you don't plan to use transceiver, and plan to use clkusr pin as general input clock pin

  • instantiate altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk))
  • You do not need to connect clkusr to mgmt_clk.
  • Just use clkusr like normal input clock pin and connect to you RTL design logic.


Thanks.


Regards,

dlim  



View solution in original post

4 Replies
Deshi_Intel
Moderator
374 Views

HI,


Can you let me know do you plan to use transceiver channel in your Quartus design ?

  • If yes, then pls don't connect clkusr to any user logic in your RTL design
  • Just provide 100MHz-125MHz clk to clkusr pin on your board


Now to your question.


1) From the Arria 10 transceiver PHY UG, it said that if there's

transceiver channels in project, it must provide one stable and about

100~125Mhz clk to CLKUSR pin for transceiver calibration. I think that

if we want to use transceiver, we must use CLKUSR pin.

  • Correct. clkusr pin is used to provide clocking to FPGA transceiver power on calibration circuitry
  • The connection is handled internally by Quartus and not visible to user. User just needs to provide external on board clocking to clkusr pin will do


2) From the UG, It said that "If you are using the CLKUSR pin for your

own logic (feeding it to the core), you must instantiate

altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock

(.clk_in(mgmt_clk));" ? What does this sentence mean?

  • This looks like a requirement to enable clkusr pin to be used for connection to user logic design and not functional as clocking input to transceiver power on calibration circuitry
  • Basically just follow the guideline to instantiate altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk)) in your top level RTL design
  • After that, you can connect clkusr pin to your own design logic


Thanks.


Regards,

dlim


lambert_yu
Beginner
369 Views

Hi dlim,

    Thanks for your answer.

    From your answer 1, I make sure that I must connect one 100Mhz-125Mhz clock to the CLKUSR pin of altera_a10_xcvr_clock_module when I use transceiver.

   From your answer 2, I have problems:

   1)  From your answer, if I do not use transceiver and I want to use CLKUSR pin as user mode clock, I must instance one altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk)), then I need declear one varibale (maybe mgmt_clk_i), and set assignment : connect mgmt_clk_i to CLKUSR pin in .qsf file. I want to know what does mgmt_clk mean?

   2) Based on1), just before I think that clk_in of altera_a10_xcvr_clock_module is output port, and I do not declear one variable (maybe mgmt_clk_i), and has no assignment about mgmt_clk_i in .qsf file, quartus will think that mgmt_clk has no implicit connect, and related logic will be optimized. In this case, I make sure I have connected one 100-125Mhz clock to the CLKUSR pin on the board and has no transceiver in my project.

  3) I have tested one case, I do not instance one  altera_a10_xcvr_clock_module, and use CLKUSR pin as general clock and feed it to fpga core, and there is no transceiver in my project, and it can work.

 4) I have tested another case, in my project, i have transceiver and connect 100Mhz-125Mhz clock to the CLKUSR pin, and instance altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk_o)) and output mgmt_clk directly in my project, I have no output on the output_pin of mgmt_clk_o.

   So, about this, I feel confused, could you help me?

Brs,

Lambert

Deshi_Intel
Moderator
342 Views

Hi Lambert,


I can sense your confusion.


You are still trying to touch on "mgmt_clk".

  • You don't need to do any extra connection to mgmt_clk.
  • When you instantiate "altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk))". It basically tell Quartus to do some internal background processing. User is not suppose to use or connect mgmt_clk to any signal (including clkusr)


Let me explain again.


(A) If you plan to use transceiver, provide on board external clock to FPGA clkusr pin

  • DO NOT connect clkusr port to anything in your RTL design anymore


(B) If you don't plan to use transceiver, and plan to use clkusr pin as general input clock pin

  • instantiate altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk))
  • You do not need to connect clkusr to mgmt_clk.
  • Just use clkusr like normal input clock pin and connect to you RTL design logic.


Thanks.


Regards,

dlim  



View solution in original post

lambert_yu
Beginner
330 Views

Hi dlim,

     I got it. Thanks for your help.

 

Best regards,

Lambert

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