FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5914 Discussions

About master and slave design of EMIF on arria 10

lambert_yu
Beginner
596 Views

Hi all,

     I face problems about master and slave design of EMIF's IPs on arria 10:

       for this design case :

       1) each emif_usr_clk signals from emif_master and emif_slave is always the same?

       2) the amm_* signals of EMIF's controller is timinged to emif_usr_clk?

       3) Could I can only use the emif_usr_clk from emif_master to timing  the amm_* signals of emif_master and emif_slave?

       4) If above problems is correct, I found that amm_rdvalid signals from emif_master and emif_slave is not synchronous and have big timing skew between each other from scope.

       5) from the example simulation result, I found that EMIF's controller can receive up to 11 requests (write/read or both), I want to that the burstcounter of read request is up to 2^7? And if I send one this read request, I can still send up to 10 write request, right?

    software : quartus pro 16.1

    fpga type : arria 10

       Could someone help me about above problems?

 

Brs,

Lambert

0 Kudos
11 Replies
AdzimZM_Intel
Employee
570 Views

Hi Lambert,


I'm Adzim. Thanks for using the Intel Community.


May I know which memory type that you used?


Thanks,

Adzim


lambert_yu
Beginner
567 Views

Hi Adzim,

 

   I am using DDR4-2666 ( MT40A512M16LY-075), thanks.

 

Brs,

Lambert

AdzimZM_Intel
Employee
534 Views

Hi Lambert,


The core clock network sharing will necessary the PLL reference clock sharing.

One of the interfaces will be a master and the other will be slaves.

The master and slaves are used the same reference clock and the output clocks signals are also same.


So you are right for your questions.

But I'm still working on to provide the answer for the question 4.


For the burstcount, it is limited to width of 1 - 11.

The minimum burst is 2^1 and the maximum burst is 2^11.

So for your design, you can create the burstcount of 2^7.

And by the way, the maximum burst length for Arria 10 external memory interface IP is 127 which is equivalence to 2^11.


You can refer to the Avalon Interface Specification document in the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf



Thanks,

Adzim


lambert_yu
Beginner
511 Views

Hi Adzim,

    

     I don't do the thing that compares the phase of the emif_usr_clk from the ddr4 master and ddr4 slave, just because I got your answer.  About the problem4, I use one async_fifo to store the ddr4 commands which generated through timinged to emif_usr_clk of ddr4 master for the ddr4 slave, but I still want to get one real reason about this problem just because the efficiency issues so that I must wait that the slowest one finishes the current burst operation before next burst operation(specially wr2rd or rd2wr switch operation).  

     Besides, for the avalon interface of the ddr4 controller, which is better for  instancing one avalon source IP or use my own logic to emunite one avalon source IP? Now I chose later, but I feel it's not good though I satisfy the timing requirement for the avalon interface.

 

Brs,

Lambert

AdzimZM_Intel
Employee
488 Views

Hi Lambert,


Switching between read and write operation can reduce the efficiency of your controller because its needs to issue the precharge and activate commands for the operation and access the bank and row.


By the way, there are methods to improve the efficiency of your controller such as Auto-Precharge Commands, Additive Latency, Calibration and so on.

You can refer to the Arria 10 EMIF User Guide in the link below on Chapter 13.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf


But its depends on your design controller to handle the traffics of the operations.


Thanks,

Adzim


lambert_yu
Beginner
460 Views

Hi Adzim,

      Is there any information for the timing skew of avl_master_ready and avl_slave_ready signals based on master and slave design of EMIF ?

 

Brs,

Lambert

AdzimZM_Intel
Employee
447 Views

Hi Lambert,


Do you have the timing report regarding to this?


Thanks,

Adzim


AdzimZM_Intel
Employee
386 Views

Hi Lambert,


Do you have any update on my last feedback?


Regards,

Adzim


lambert_yu
Beginner
384 Views

Hi Adzim,

 

     Just because the time gap got from the scope between avl_ready_s and avl_ready_m, the time gap got from the scope between avl_read_valid_s and avl_read_valid_m are all not one a fix value, so I can not privide the timing skew.

 

Brs,

Lambert

AdzimZM_Intel
Employee
361 Views

Hi Lambert,


I put the case to closure since you already found the solution for your issue.


Feel free to file a new case if you encounter a new problem.


Regards,

Adzim


AdzimZM_Intel
Employee
361 Views

Hi Lambert,


I put the case to closure since you already found the solution for your issue.


Feel free to file a new case if you encounter a new problem.


Regards,

Adzim


Reply