About the DDR2 High Performance IP problems

[Altera_Forum]

The high performance DDR2 IP core which is generated by Quartus7.1 does not work well in the Modelsim6.1 simulation. The local_write_req is asserted, but the local_wdata_req does not give a response to the requirement. And the reset_request_n is not asserted indicates the PLL is not locked. I do not know why.  

The refresh signal is initiated shows the IP function is working well but with no response for the input signal.  Could someone help me to solve this problems? Some pictures is eclosed for your reference. Thanks in advance.

[Altera_Forum]

This problem is also solved. I used the IP_CORE_NAME.vhd and IP_CORE_NAME.vho concurrently, so it the reason why the ip core does not work well. Delete the IP_CORE_NAME.vhd from the project can solve this problem. Thanks