About transceiver power-up calibration of arria 10

[lambert_yu]

Hi sir,

    I am facing one confused problem about power-up calibration sequence of arria 10:

   From the transceiver section 7.3, It said that " If a system has an FPLL, an ATX PLL, and channels, the fpll cal_busy signal goes low first. The ATX PLL cal_busy signal goes low after the channel' tx_cal_busy and rx_cal_busy signals". But From the figure 284, the sequence is ATX_PLL Calibration --> fPLL Calibration ---> RX & TX PMA calibration, I think that means: ATX PLL cal_busy goes low first, then fPLL, finally, RX&TX cal_busy.  Right? If so, is not the content before and after controdictory?

  Best regards,
Lambert

[CheePin_C_Intel · Accepted solution]

Hi,

As I understand it, you have some inquiries related to the calibration sequence for the A10 XCVR blocks. For your information, you should refer to the Figure 284 and Figure 286 for the calibration sequence which should be ATX -> fPLL -> PMA. There should be some typo at the initial description. Sorry for the inconvenience.

Please let me know if there is any concern. Thank you.

[lambert_yu]

Hi,

   So from your view, I think that the switch to low sequence of cal_busy is ATX--> fPLL-->PMA according to the figure 284 & 286, right? If so, I think that's reasonable.

B.R.

Lambert

[CheePin_C_Intel]

Hi,

Yes, your understanding is correct. The right sequence is ATX -> fPLL -> PMA. Thank you.

[CheePin_C_Intel]

Hi,

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.