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RBLUM7
Beginner
95 Views

Access AN639 Example Design files

I'm trying to download and look at the Design Examples from application note AN639 (Inferring Stratix DSP Blocks for FIR Filtering Applications). I can download the PAR files, but am not able to extract readable rtl (verilog or VHDL) from the files (using Quartus) following the steps on the webpage. Is there an alternative way I can access these files?

I registered for a premier account, and received an email saying I was accepted. I'm an engineer at BAE Systems Manassas VA.

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sstrell
Honored Contributor II
46 Views

The .par file should create a new project when you double-click it or you can install the .par file in the New Project Wizard as it instructs.

 

https://fpgacloud.intel.com/devstore/platform/16.1.0/Standard/stratixv_dsp_fir_verilog_basic_fir/

 

At what point are you having an issue with reading the files?

 

#iwork4intel

RBLUM7
Beginner
46 Views

​I tried again, using a different version of Quartus, 15.1 (I'm running linux, and our site maintains multiple versions), and it worked this time.  I was able to unpack all.  I'm not sure why that made a difference or if that was even the problem, but I'm good for now.    Thanks anyhow, for the help.

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