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Access to BAR0 qsys pci-e in the Cyclone IV FPGA on the board DB4CGX15

Honored Contributor II

Hello, dear friends!  

I address the following request.  

There is a charge on which the Cyclone IV and PCI-E-endpoint interface. It is necessary to arrange the transfer of data to a PC for further processing on the FPGA, and then send them back to your PC. Written kernel module linux, which writes to BAR0 register value. FPGA is necessary to take this value, add to it and get back to deuce. The problem is that I can not reach out PLISiny BAR0 register, in order to modernize it. Attempts were made to create your own module in QSYS (Quartus II web ed.) To connect on Avalon MM slave interface to the conclusion BAR 0 Avalon MM Master, and Avalon MM Master concluded txs in pci-e. All to no avail. Attempt was made to search the register in the generated files to Qsys inside the module control bus Avalon MM write the value of the addition to the original in the bus on the way out Bar0.  

No results too. As a PCI-board device is perceived in the OS correctly.  

Qsys module code and image schemes are given below: 


`timescale 1 ps / 1 ps module bvs_pci_server1bar# ( parameter AUTO_CLOCK_SINK_CLOCK_RATE = "-1" ) ( input wire serv_bar1_0_addr, // avalon_slave.address input wire serv_bar1_0_read, // .read output wire serv_bar1_0_waitreq, // .waitrequest input wire serv_bar1_0_write, // .write output wire serv_bar1_0_readd, // .readdata input wire serv_bar1_0_writed, // .writedata input wire serv_bar1_0_burstcnt, // .burstcount input wire serv_bar1_0_byteen, // .byteenable output wire serv_bar1_0_readdatavalid, // .readdatavalid output wire serv_txs_addr, // avalon_master.address output wire serv_txs_byteen, // .byteenable input wire serv_txs_readd, // .readdata output wire serv_txs_read, // .read output wire serv_txs_write, // .write input wire serv_txs_readdatavalid, // .readdatavalid input wire serv_txs_waitreq, // .waitrequest output wire serv_txs_chipsel, // .chipselect output wire serv_txs_burstcnt, // .burstcount output wire serv_txs_writed, // .writedata input wire serv_rst, // reset_sink.reset input wire serv_clk, // clock_sink.clk output wire serv_irq // interrupt_sender.irq ); // TODO: Auto-generated HDL template assign serv_bar1_0_waitreq = 1'b0; assign serv_bar1_0_readd = 64'b0000000000000000000000000000000000000000000000000000000000000000; assign serv_bar1_0_readdatavalid = 1'b0; assign serv_txs_burstcnt = 7'b0000000; assign serv_txs_addr = 20'b00000000000000000000; assign serv_txs_chipsel = 1'b0; assign serv_txs_write = 1'b0; assign serv_txs_read = 1'b0; assign serv_txs_byteen = 8'b00000000; reg _value = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg _irq = 1'b0; reg _txs_writed = 64'b0000000000000000000000000000000000000000000000000000000000000000; always @(posedge serv_clk) begin if(serv_bar1_0_readd != _value) begin _value <= serv_bar1_0_readd; _txs_writed <= serv_bar1_0_readd | 64'h00000002; _irq <= 1'b1; end else _irq <= 1'b0; end assign serv_value = _value; assign serv_irq = _irq; assign serv_txs_writed = _txs_writed; endmodule
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