Address problem of custom IP

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Address problem of custom IP

799 Views

I'm a freshman learning Qsys and Avalon-MM. And I'm making a master and a slave to test typical transfer function. But, I find when I write 4 words to 4 addresses from the master, while, the slave recieve one address.

I don't know why it always fails to insert images...

The signals:

master address send: 1...2...3...4...5...6...7...8...

address the slave recieve: 1................2.................

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.