Address problem of custom IP

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Address problem of custom IP

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I'm a freshman learning Qsys and Avalon-MM. And I'm making a master and a slave to test typical transfer function. But, I find when I write 4 words to 4 addresses from the master, while, the slave recieve one address.

I don't know why it always fails to insert images...

The signals:

master address send: 1...2...3...4...5...6...7...8...

address the slave recieve: 1................2.................

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