Agilex 5 E-Series FPGA Triple Speed Ethernet SGMII with PHY Management

[Nicole04]

Good day,

I would like to use the Triple Speed Ethernet IP Core for 16 10M/100M/1G Ethernet ports on the Agilex 5.

I am unable to set up the IP core to use the transceiver and have a PHY management bus (MDIO, MDC). How can it be set up for this?

The one option uses GTS transceivers, but then there is no MDIO option.

Thank you for your assistance.

Kind regards,

Nicole

[paveetirrasrie_Intel]

HI Nicole,

May I know which Quartus version you're working with?

Quartus version 24.1 GTS Transceiver does not have an option to enable MDC/MDIO. Planned to have the option in future releases.

Regards,

Pavee

[Nicole04]

Hi Pavee,

I am using Quartus version 24.2. When will this update be available? 

Which clocks are required for the TSE with SGMII?

Regards,

Nicole

[paveetirrasrie_Intel]

Hi,

I'm unable to give you a exact release date but you may expect it in coming release.

rx_clkena - Receive clock enabler for SGMII 10M/100M operating speeds.

tx_clkena - Transmit clock enabler for SGMII 10M/100M operating speeds.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello Nicole,

I believed I have answered all your query. I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Altera experts.

Otherwise, the community users will continue to help you on this thread. 

Thank you.