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Altddio

Altera_Forum
Honored Contributor II
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I'm using the megafunction ALTDDIO as a receiver which requires the input data to be centered aligned to the rising and falling source clock. Unfortunely I have learned the source and data are going to be coming in edge aligned. I've been trying to find a way to delay the input clock by 90 degrees. I have looked into using the PLL, but because of the wide range of source clock (25MHz to 165MHz), the PLL won't be able to lock onto it so this is not an option.  

 

Is there a way to delay the clock or data so that they meet the ALTDDIO requirement?  

 

Your comment is much appreciated.
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