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Altera Compact flash IP Core Performance

Altera_Forum
Honored Contributor II
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Hi, 

 

I am designing a data acquisition system with Altera FPGAs. My system contains a Compact Flash IP core and Nios II processor. My problem is I can’t read and write Compact Flash more than 1MBps with FAT32 file system. I clock the Nios processor at 100MHz and target FPGA is Stratix 1s10.could anybody tell me that what the max performance of the Altera CF ip core is? Unfortunately Altera’s documents for this core is too vague and it is not giving you much information. If IP core is capable enough to cope with data more than 1MBps could you tell me how I can achieve higher speeds?  

 

I tried my design with different CF from 1GB to 32GB. 

 

Thanks in advance  

Aidan.
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Altera_Forum
Honored Contributor II
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That is about all you are going to get out of it. It is stuck at PIO Mode 0. 

 

Check WikiPedia out for the different modes available: 

 

http://en.wikipedia.org/wiki/programmed_input/output 

 

There have been suggestions to try altering the timing in the PTF/SOPC file however I tried it and did not gain anything as far as performance goes. 

 

Does anyone else have any suggestions? I would like to use at least PIO Mode 4 or higher.
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Altera_Forum
Honored Contributor II
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I found the best way to increase the CF performace is to implement the different level of caching. You don't need to write to CF each time you received the data. simply buffer them on RAM(say 8 MB of data) and then burst it into compact flash. you can also use DMA engines to transfer the data into Ram while you are writing into CF.(Real Parallel) it should be a little clever algorithm which manage these buffers. performane probably improves by 5. also use industrial CF.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

 

I am designing a data acquisition system with Altera FPGAs. My system contains a Compact Flash IP core and Nios II processor. My problem is I can’t read and write Compact Flash more than 1MBps with FAT32 file system. I clock the Nios processor at 100MHz and target FPGA is Stratix 1s10.could anybody tell me that what the max performance of the Altera CF ip core is? Unfortunately Altera’s documents for this core is too vague and it is not giving you much information. If IP core is capable enough to cope with data more than 1MBps could you tell me how I can achieve higher speeds?  

 

I tried my design with different CF from 1GB to 32GB. 

 

Thanks in advance  

Aidan. 

--- Quote End ---  

 

 

 

 

can you send your code to me?i have trying to write this code like you but never have win....thank you
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