10-03-2013 02:54 PM
Hello All,The Altera Frame Buffer IP takes the frame from its Avalon ST sink and stores it to the DDR2 then read it back and output it via its Source. Can anyone confirm that at the same time the data output (from the FB Source) and the data input (in the FB sink) represent respectively the old frame and the current frame ? And those 2 frames are they synchronized ? I mean are they output at the same time ? And if there a latency between the two frames how can I eliminate it ? 2 SCFIFOs will do it I think ? http://zupimages.net/up/3/623670993.png Best regards
10-03-2013 04:49 PM
This component always buffers entire frames. So, the output is always at least 1 frame older than the input, and there is always at least 1 frame quantum of latency.If you are simply trying to resolve timing differences between your input and output sides, yes maybe you can get away with onchip FIFO. If you were drawn to the Frame Buffer because you hoped it was a really big FIFO working via offchip memory, sadly it is not.