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Altera MAX 10 Avalon SPI Core as Master Issue

Honored Contributor II



Just for experimentation I am trying to interface two DE10 lite boards, one as a SPI master and one as SPI Slave. 

I have tested the Avalon SPI slave core successfully by interfacing with Rasberry pi acting as a SPI master. 


I am running into a few issues when testing the Avalon SPI core as a Master.  


I have done the following till now: 


Instantiated and Synthesize NIOS + Spi Master core as a QSYS system. Exported the SPI conduit and connected them to GPIO pins. The core is configured at SCLK 1 Mhz. I program the FPGA with the elf. 

Logic analyser is connected to the GPIO pins 


In NIOS eclipse : I have extended the small hello world program and included the SPI related headers ( Registers and the SPI command files) 


When I issue the command : "alt_avalon_spi_command(SPI_BASE, 0, 1, &r_data, 0, 0, 0)" I see absolutely no output on the GPIO lines.  


Any suggestions on what could be going wrong ? 





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