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I am triying to use the remote updater block from Altera. When I setup it (PAGE select, AnF bit, watchdog) and set the signal reconfig to '1', the FPGA does not do anything
-I setup the page, the AnF register, the watchdog value and Watchdog enable, and then I setup to one the reconfig signal and it does not do anything. -The clk input freq is 10Mhz -I check the status register (000) at the beginning after reset and the 5 bits are in '1' value ( all error), i check it later and it does not change. -If i read the registers that i write (watchdog for example) appear to have a right value. -The eeprom is EPCQ128 -Quartus 14.1 Could you give me any advice to make it work? Thanks- Tags:
- Nios® II Processor
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Hello,
Is it possible for you to share your design? I will see if I can help you. In past, we successfully used Remote Status update block for Cyclone IV device. Cheers, Bhaumik- Mark as New
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Its impossible to share the design, company rights.
One detail that i forgot was that it is implementid in a qsys system with NIOS II- Mark as New
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--- Quote Start --- Its impossible to share the design, company rights. One detail that i forgot was that it is implementid in a qsys system with NIOS II --- Quote End --- Ok. No problem. We followed steps similar to provided in http://www.altera.com/literature/an/an603.pdf. Cheers, Bhaumik
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