Altera VIP simulation and the ref. design no.427

[Altera_Forum]

Hi, I'm new here. Glad to meet you. 

 I have 2 question about the latest (ver.8.0) of the Altera VIP (Video & Image Processing Suite)  1) Is there anyone here successfully simulating the VIP functions?.  The MegaCore wizard does not generate simulation models, test bench etc. I have to see if the VIP functions before implementing it on the hardware. Please advice!  2) Is there anyone successfully implementing (to generate SOF file) the ref. design for the VIP ver.8.0 as described in the app. note no.427 <http://www.altera.co.jp/literature/an/an427.pdf>  When I tried to 'Start Compilation' (after re-generating the Nios-2 system using SOPC builder), the Quartus II stopped with 12 errors and hundreds of warnings. I am wondering if the ref. design really function.... Please advice!  Thanks in advance!  ----------errors-------------------- Error: Node instance "my_alt_vip_clip" instantiates undefined entity "alt_vip_clip_GNVO2UKTWW" Error: Node instance "my_alt_vip_cpr" instantiates undefined entity "alt_vip_cpr_GNJQ4YFLPE" Error: Node instance "my_alt_vip_cpr_1" instantiates undefined entity "alt_vip_cpr_GNRW3PSMJV" Error: Node instance "my_alt_vip_crs" instantiates undefined entity "alt_vip_crs_GNE6NPS5F5" Error: Node instance "my_alt_vip_csc" instantiates undefined entity "alt_vip_csc_GNOSDMRPPF" Error: Node instance "my_alt_vip_dil" instantiates undefined entity "alt_vip_dil_GNHDD6LS33" Error: Node instance "my_alt_vip_mix" instantiates undefined entity "alt_vip_mix_GNWZPL24MV" Error: Node instance "my_alt_vip_scl" instantiates undefined entity "alt_vip_scl_GNF4N44SOZ" Error: Node instance "my_alt_vip_tpg" instantiates undefined entity "alt_vip_tpg_GNUAHFWJD4" Error: Node instance "my_alt_vip_vfb" instantiates undefined entity "alt_vip_vfb_GNSVPB2QIW" Error: Quartus II Analysis & Synthesis was unsuccessful. 10 errors, 83 warnings  Error: Peak virtual memory: 308 megabytes  Error: Processing ended: Fri Sep 26 07:10:29 2008  Error: Elapsed time: 00:04:19  Error: Total CPU time (on all processors): 00:00:53 Error: Quartus II Full Compilation was unsuccessful. 12 errors, 83 warnings ---------------------------  ---------warnings------------- Warning (10236): Verilog HDL Implicit Net warning at altmemddr_auk_ddr_hp_controller_wrapper.v(243): created implicit net for "mem_dqsn_en" Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1124): object "ac_h_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1125): object "ac_l_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1126): object "ac_h_2r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1127): object "ac_l_2r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1134): object "ac_2x_retime" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1135): object "ac_2x_retime_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1124): object "ac_h_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1125): object "ac_l_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1126): object "ac_h_2r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1127): object "ac_l_2r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1134): object "ac_2x_retime" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(1135): object "ac_2x_retime_r" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(2325): object "global_reset_ams_n" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altmemddr_phy_alt_mem_phy_ciii.v(2326): object "global_reset_ams_n_r" assigned a value but never read Warning: Variable or input pin "datad" is defined but never used Warning: Variable or input pin "datad" is defined but never used Warning: Variable or input pin "datad" is defined but never used Warning: Assertion warning: oe input port is not connected Warning: Assertion warning: oe input port is not connected Warning (10034): Output port "wb_dat_o[31]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[30]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[29]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[28]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[27]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[26]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[25]" at opencores_i2c_master.vhd(16) has no driver Warning (10034): Output port "wb_dat_o[24]" at opencores_i2c_master.vhd(16) has no driver ............... --------------------------

[Altera_Forum]

I am hoping you found a solution to this problem, as I am encountering the exact same error message. 

 --  William Guynes

[Altera_Forum]

It appears this error occurs if the user executing the Quartus II IDE does not have Administrator permissions. 

 Is it Altera's position that all FPGA developers have Administrator access? (to the local machine, not the domain)  If not, what sub-permissions must the developer account be granted in order to successfully compile?