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Honored Contributor II



I am trying to instantiate the altera_fp_functions ip core into my design and I have included the libraries necessary. 

i.e library altera_mf;  

use altera_mf.altera_mf_components.all;  


The name I have given for the core and the entity work uses the same name "add_int32_logic". 

Yet, I am shown an error stating "Error (10481): VHDL Use Clause error at add_int32_logic_top.vhd(41): design library "work" does not contain primary unit "add_int32_logic"" 


Why is this happening? Is there any other library that I am supposed to use in my deisgn?
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