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Altmemphy

Altera_Forum
Honored Contributor II
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Hi all, 

 

Now I'm using ALTMEMPHY as physical layer interface between my DDR2Controller to DDR2SDRAM on CycloneIII.But when "resynchronisation_successful" signal of ALTMEMPHY is high,my controller cannot read correctly data from DDR2SDRAM.Does anyone know what happen in my project?Any way,can you guide me to add mem_dq,mem_dqs signals of ALTMEMPHY to SignalTapII? 

I really need your help,thanks in advance. 

 

npak.
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Altera_Forum
Honored Contributor II
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Hello, 

 

basically, double data rate signals aren't accessible to SignalTap. They only exist at the DDR2 I/O pin interface. You need an oscilloscope or fast logic analysator to check DDR2 timing and data content. 

 

You say, you can't "read correctly data from DDR2SDRAM" after "resynchronisation". I assume, this is neither the case before PLL reconfig? The point is, that DDR2 calibration requires complex interaction between your controller and ALTMEMPHY. It depends particularly on your controller's ability to write and read test data when required. I think this isn't an easy design problem and can fail in many ways. I preferred using the Altera HP DDR2 controller IP. 

 

However, if you decide to build your own controller, which could be necessary to meet particular design requirements, then simulation gives you insights to internal signal flow and DDR2 interface without fast test equipment. But due to the complex design, also simulation isn't done in a moment, it's hard work. 

 

Regards, 

Frank
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Altera_Forum
Honored Contributor II
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Hi Frank, 

 

I also simulate my project on ModelSim and all thing is OK. 

What does it mean when "resynchronisation_successful" is high? 

Thank for your help, 

 

Npak
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Altera_Forum
Honored Contributor II
385 Views

Hello, 

 

I think resynchronisation_successful is success for one of several steps in recalibration. I apologize, that I didn't care for the individual calibration status signals from Altmemphy, cause HP controller encapsulates them. The important point is to reach the final user_mode_ready state. 

 

But if an identical configuration as you are operating in hardware could be verified in simulation, I would assume a hardware issue. Did calibration complete succesfully in your hardware version? If so, the basic memory interface function seems to be operational, but data errors for data different from train pattern could occur anyway. 

 

Regards, 

Frank
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Altera_Forum
Honored Contributor II
385 Views

Hello Frank, 

 

In my project, "ctl_usr_mode_rdy" signal also is turned on.I see this signal in SignalTapII. 

But up to now,i still cannot read correctly data. 

Can you give me an advice? 

 

Thank a lot for your help, 

 

Npak
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Altera_Forum
Honored Contributor II
385 Views

Hello, 

 

what it exactly wrong with your data and how did you check them? 

 

Regards, 

Frank
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Altera_Forum
Honored Contributor II
385 Views

Hi, 

 

The ctl_usr_mode_rdy just means the ALTMEMPHY finished calibration, does not mean the calibration is successful. 

 

Please check if the DDR2 pins connected correctly and check the DDR2 pin termination. 

 

Regards, 

Harold
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Altera_Forum
Honored Contributor II
385 Views

Hi all, 

 

Thank for your advices, 

I find out that I met this error due to mem_odt signal.I didn't activate mem_odt before. 

Now I can make our controller work correctly. 

 

Thank all again, 

Npak
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