Based on the snapshot you shared, it shows a syntax error which means the issue is in the line or statement in the code which does not conform with the Verilog syntax rules. I would recommend you check first on any possible syntax error in the code or upgrading the Verilog version to the latest one and see if the issue is resolved.
As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
