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agula
New Contributor I
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Aria 10 PCIe Avalon Stream SR-IOV Example Simulation

Hi,

I am unable to get the example design up and running with the Aria 10 PCIe express example design with SR-IOV. This is covered in Section 2 of the following documentation:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

I am simulating using model sim. After invoking ld_debug, I am getting hierarchy errors saying the following:

 

Thank you

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