Aria 10 PCIe Avalon Stream SR-IOV Example Simulation

[agula]

Hi,

I am unable to get the example design up and running with the Aria 10 PCIe express example design with SR-IOV. This is covered in Section 2 of the following documentation:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

I am simulating using model sim. After invoking ld_debug, I am getting hierarchy errors saying the following:

Thank you

[mark_lee]

hi agula

where can i downloal the SR-IOV example for  ariia10 device?

thanks!

[agula]

Hi,

Should be in the IP folder of your Quartus download. The examples should be marked SRIOV.  I used the 2 PF and 4VF example design. If you load the .qsys file into platform designer you should be able to generate a test bench for the system.

[mark_lee]

Hi  Agula

    Thanks for your help .

[mark_lee]

hi agula 

   i simulating in ModelSim  and get an same errors with you