I am unable to get the example design up and running with the Aria 10 PCIe express example design with SR-IOV. This is covered in Section 2 of the following documentation:
I am simulating using model sim. After invoking ld_debug, I am getting hierarchy errors saying the following:
Should be in the IP folder of your Quartus download. The examples should be marked SRIOV. I used the 2 PF and 4VF example design. If you load the .qsys file into platform designer you should be able to generate a test bench for the system.