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Arria 10 DDR4 SODIMM calibration fails occasionally. How to remove this bug?

IKovr1
Beginner
284 Views

We have 2 Banks DDR4 SODIMM on our board connected to 10AX115H3F34E2SG. After Arria10 configuration we start Calibration process for both memory banks. For Menory Bank A calibration always pass, but for Bank B often calibration don't pass . Sometimes an additional Reset signal corrects the situation. Sometimes we swap DDR4 SODIMM . We have 2 independent memory controllers with a common Reset signal, but if memory is removed from Bank B, then memory bank A stops calibrating. May be you have ref. design for two 64 bits DDR4 SODIMM memory banks ? Settings for both our memory controllers now the same. Frequency which we can reach in our design 900Mhz for both banks.

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4 Replies
sstrell
Honored Contributor III
143 Views

I'm assuming the 900 MHz you refer to is the external memory speed. Are you running your user logic at half or quarter rate (and meeting timing)?

 

Have you considered enabling the EMIF Debug Toolkit feature so you can see the results of calibration and figure out where the issue may be? See this online training for details:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1124.html

 

#iwork4intel

IKovr1
Beginner
143 Views

Thank you for reply.

 

We running user logicat quarter rate (225 MHz)

Yes we know about EMIF Debug Toolkit .

At the moment when the bank is not calibrated, we see deviations along some lines.

But when the bank starts to calibrate after a series of Reset signals, then we see that everything is normal.

This situation occurs randomly.

At first we will try decrease memory frequency and use half rate at user logic

 

Best Regards

Igor

 

sstrell
Honored Contributor III
143 Views

Make sure you run the DDR timing report in the Timing Analyzer to verify that you are meeting timing. This sounds like a potential timing issue.

 

#iwork4intel

IKovr1
Beginner
143 Views

Probably I should clarify. We now have more than one PCB we have 180 same boards. On some boards, bank B is calibrated stably at 900 MHz; on another number of PCBs, bank B is not calibrated continuously. sometimes yes, sometimes no. On the third, it does not calibrate at all. Today we decrease the frequency at the input oscillator so that the total became 600 MHz and those banks that were not calibrated are calibrated. It is very likely that in one batch of PCB there are differences in impedances on data lines and memory addresses. FPGA design is always the same.

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