Community
cancel
Showing results for 
Search instead for 
Did you mean: 
mvemp
Novice
644 Views

Arria 10 DDR4 external memory interface

I am designing my IP in OpenCL. However, I am trying to analyse the maximum vector length of data which can be fetched from DDR4 present on Arria 10 GX board.

 

Where can I find the IP responsible for fetching data from DDR4. Is there a hard IP present on Arria 10 chip wrt DDR4? What is bitwidth between DDR4 and memory controller?

0 Kudos
4 Replies
NurAida_A_Intel
Employee
97 Views

Hi Sir,

 

Good day to you.

 

Intel offer PCI Express DMA Reference Design Using External Memory that uses an external memory connected to the Intel memory controller that can access up to 128 MB of on-board external memory. The read DMA moves the data from the system memory to the external memory. The write DMA moves the data from the external memory to the system memory.

 

You may refer to page 10 of this handbook for more details on how to run the reference design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an708.pdf

 

You may also refer to this Intel wiki page where user can download the Arria 10 Gen3x8 AVMM DMA reference design with DDR4 controller to access external DDR4 on board memory. Hope this is helpful.

https://fpgawiki.intel.com/wiki/Reference_Design:_Gen3x8_AVMM_DMA_with_external_DDR4_-_Arria_10

 

Thanks.

 

Regards,

NAli1

mvemp
Novice
97 Views

Hello NAli1_Intel,

 

Thank you for the reply. Thank you for the reference documents.

 

1) If Avalon DMA IP only access 128 MB of external DRAM, is it beneficial to use it for Arria 10 GX board which contains 2GB on board DRAM?

 

2) In the document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_overview.pd..., page 22, it is mentioned "Intel Arria 10 devices offer massive external memory bandwidth, with up to seven 32- bit DDR4 memory interfaces running at up to 2,400 Mbps". Does it mean the bandwidth between Arria 10 and one channel of DRAM is 32 x 7 bits?

 

 

HRZ
Valued Contributor II
97 Views

1) 128 MB is probably a typo. I am sure the Hard IP supports at least up to 8 GB per DIMM, probably even more.

2) The physical interface between the FPGA and each DDR3/4 memory DIMM is 64 bits (72 bits with ECC). The theoretical peak bandwidth per DIMM is (64 bits x memory clock). e.g., it will be ~17 GB/s (15.9 GiB/s) per DDR4-2133 MHz DIMM which is typically used on Arria 10 boards.

NurAida_A_Intel
Employee
97 Views

Hi HRZ,

 

Thanks for the useful information. Appreciated the sharing.

 

Hi mvemp,

 

"Intel Arria 10 devices offer massive external memory bandwidth, with up to seven 32- bit DDR4 memory interfaces running at up to 2,400 Mbps" means you can build 7 controllers with 32- bit DDR4 memory interfaces running at up to 2,400 Mbps in Arria 10 device.

 

Thanks

 

Regards,

NAli1

Reply