Arria 10 EMIF DDR4 slow write

[rled64]

Hello community,

I am working on Terasic HAN Pilot Plateform based on Arria 10 device. This plateform includes two DDR4 SDRAM x16 4Gb 1066MHz modules that gives a single memory of 32b wide DQ and 8Gb.

I want to access this module from FPGA with an Intel External Memory Interface (EMIF) IP.

I used recommanded EMIF configuration from Terasic for this board and DDR4 memory and wrote my own avalon-MM burst controller in order to access EMIF.

The avalon-mm has a "burstcount" signal which is 7 bit wide which allows up to  2⁷ = 127 burst, and a data bus which is 256bit wide, so 8 times the 32 bit bus width from DDR4 module.

Since the module has a theoretical bandwidth of 2133MT/s in 32 bits, this on my amm controller side, I have to drive at 266 MHz the databus of 256 bits. 

My issue is that, when I write for instance with a burstlength of 16, I have 16 "waitrequests" going high for 8 clock period @ 266MHz. Meaning I have a datarate 8 times slower : 266/8 with 256 bit bus on EMIF AMM side or 2133/8 with 32 bit bus on DDR4 side ! See the signaltap diagram below :

As you can see I perform 16 writes waiting each for the the waitrequest to go low in order to proceed with next write of the burst.

My wonder here, is that I am actually performing 16 burst writes with a burstlength of 8, so a total of 128 writes... Why do I that ? Because here is what I found in the EMIF advanced mode register settings : 

We can cleary see that the burst length is set to "Fixed BL8" which I suppose means that I cannot change this length of 8 through the amm-burstlength. This explains why I would have a waitrequest of 8 clock period @ 266 MHz, this is just bursting the 8 writes during this time. Am I right ? I will check this of course, but I want to be sure that this is the intended write, and I don't understand why there is this confusing amm_burstlength while the burstlength is fixed and appears to not be editable.

Thanks in advance for enlightenment !

Roman

[AdzimZM_Intel · Accepted solution]

Hi Roman,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

I'm checking with you if you still have the question on this topic since you have found the answer in the other thread.

Thank you for your feedback.

Regards,

Adzim