Arria 10 EMIF debug interface register description

[MUrba10]

Hello!

I'm trying to understand how to use EMIF debug interface for Arria 10 onboard, i.e. without using JTAG and Quartus. My goal is to connect Arria 10 EMIF controller avalon calibration bus to NIOS which is already present in my system and read calibration status and other information from EMIF.

Quartus generates three example source files for this purpose "emif_export.c", "emif_export.h" and "main.c". However it is not clear from these files how to interpret received information. For example, the structure debug_summary_report_t in the file "emif_export.h " has fields error_stage, error_group, error_code, error_info but it is not clear how to interpret their values.

Is there any document or user guide which gives explanation or even better register map for peripheral behind EMIF cal_debug bus?

Thank you!

[NurAida_A_Intel]

Hi MUrba10,

Thank you for joining this Intel Community.

You may refer to Chapter 3 .Intel Arria 10 EMIF IP End-User Signals of this user guide (attached link) on page 52 which describe each of the interfaces and their signals, by protocol, for the Intel Arria 10 EMIF IP. While ways to debug Arria 10 EMIF IP is explained in Chapter 13.7. Debugging Intel Arria 10 EMIF IP (page 439) of the user guide.

User guide link : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf

Hope this helps.

Thanks

Regards,

NAli1

[MUrba10]

Hello NAli1_Intel,

Thank you for your answer.

I've read this document already, but I wasn't able to find the answer to my question. Yes, in Chapter 3 there is a description of calibration interface signals, but no information about register map behind this interface.

In this document there is a Chapter 14.7.2.2 Access Protocol where there is some general information. For example there is a description of a data structure used to communicate with calibration peripheral:

typedef struct_debug_data_struct { ...

// Command interaction

alt_u32 requested_command;

alt_u32 command_status;

alt_u32 command_parameters[COMMAND_PARAM_WORDS];...

} 

But not much information beyond that. What I need is more thorough description of registers and values used in this communication protocol.

Thank you!

[NurAida_A_Intel]

Hi MUrba10,

I believed you are requesting for the register mapping. If my assumption is correct then I am sorry to say that we don't provide the register mapping for DDR4. Actually, the C header file( "emif_export.c", "emif_export.h" and "main.c") is provided to user in order for user to use the On-Chip debug which allows user logic to access the same debug capabilities as the External Memory Interface Toolkit and monitor the calibration results of EMIF.

But there is a *readme.txt file included when the IP HDL files are generated (see attached *readme.txt for reference) that have the instructions on how to use the software are available in the following file: :

<variation_name>/altera_emif_arch_nf_<version number>/<synth|

sim>/<variation_name>_altera_emif_arch_nf_<version

number>_<unique ID>_readme.txt.

In the *readme.txt file, there is a section called "Using the On-Chip Debug Interface" that describes more details.

Also, here is some additional info for you on the Intel PSG YouTube of Using the Soft Nios Processor to debug Arria 10 External Memory Interface, which is at:

https://www.youtube.com/watch?v=pMJTjZfqyrM

Hope this helps.

Thanks

Regards,

NAli1

[NurAida_A_Intel]

posted a file.

[MUrba10]

Hello NAli1_Intel,

Thank you for your answer.

[NurAida_A_Intel]

Hi MUrba10,

If you want to consider using DDR3 protocol, then you may refer to Chapter 1.14. Register Maps (page 46) of this EMIF handbook for the register mapping. --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf#page=46

Again sir, I am sorry for any inconvenience that I may caused you .

Thanks

Regards,

NAli1

[MUrba10]

Hello NAli1,

No problem, thank you for your help.