FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6379 Discussions

Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.


This is an issue sharing:

When inserted Arria 10 PCIe Gen3 design endpoint card into a Gen4 capable Host/CPU, the PCIe link might keep cycling between L0->Recovery.Rcvlock->Recovery.Rcvconfig->Recovery.Idle->L0->Recovery.Rcvlock.....

Data Link Feature Exchange is not part of PCIe Gen3.0 specification, and it is an optional feature per PCIe Gen4.0 Specification.
The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC.
When this happens, no error is reported by the Intel® Arria® 10 FPGA. This is an expected behaviour.

To work around this problem, disable the Data Link Feature Exchange in PCIe 4.0 system BIOS [Base spec 4.0 chapter Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware.

1 Reply

Thanks for posting this advice.

We have run into the same issue above, and it was confirmed that this issue exists also in the Arria V GZ device.


The work around is successful and is implemented on BIOS in most cases.