Hi,I am designing user logic to access DDR4 Memory on Arria 10 GX FPGA Development Kit. I instantiated EMIF in Qsys. It has following parameters: DQ width: 72 Row address width: 15 Column address width: 10 Bank address width: 2 Bank group width: 1 Now, ctrl_amm_0 (Avalon Memory Mapped Slave) for EMIF IP has following signals: address: 25 burstcount: 7 byteenable: 72 read: 1 readdata: 576 readdatavalid: 1 ready : 1 write: 1 writedata : 576 I can understand larger readdata/writedata size as it works at quarter rate. But what I do not understand is addressing method. Slave only expects 25 bits as address which is sum of row and column address. How do I specify bank address and bank group? Thanks and Regards, Parthiv
Hmm. What do you have the Address Ordering option set to on the Controller tab in the parameter editor?