FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5952 Discussions

[Arria 10 GX Development Kit] PCIe for External Memory BAR4 length

Altera_Forum
Honored Contributor II
891 Views

Hello everyone, 

 

I've been developing a PCIe-based co-processor system using Arria 10 GX Dev Kit and I am having some trouble configuring a proper BAR4 size to address all slaves connected to the PCIe DMA IP. For data transfers from the host to the FPGA, I am using the a Linux DMA driver adapted from the altera_dma driver provided along with the reference design (PCI Express Avalon-MM DMA Reference Design). 

 

My system interconnection is as follows: 

 

ep ip start - end addr 

PCIe Hard IP (DUT) 

|--------------------------------- EMIF(ctrl_avmm_0) 0x0000_0000 - 0x0FFF_FFFF (256 MB) (28bits) 

|--------------------------------- ONCHIP_MEM 0x5000_0000 - 0x0000_001FF (512 B) (9 bits) 

|--------------------------------- CO-PRO 0x1000_0000 - 0x0000_003FF (1024 B) (10bits) 

 

TOTAL ADDRESSES EXPECTED: 0x1000_0000 + 0x0200 + 0x0400 = 0x10000600 

 

For this configuration, Qsys calculates a 31bit size for BAR4 (0x4000_0000), configure as a 64bit non-prefetchable memory. This length should be enough to cover all EMIF addresses, plus the CO-PRO and ONCHIP. Therefore, from my DMA driver I should be able to read or write single words (iowrite32, ioread32) to any offset from the BAR4 start address, right? 

 

For example, if I wanted to write a 32bit word to the first position on the ONCHIP memory I should: 

 

int onchip_base = 0x50000000; 

int data = 0xAB; 

__iomem * ptr = pci_ioremap_bar (pdev, 4); 

iowrite32(data, ptr + onchip_base); 

... 

 

However, using this strategy I am able to write or read positions on EMIF and CO-PRO (addresses smaller than 0x40000000), but not on the ONCHIP_MEM. I believe the problem is because the base address for the ONCHIP_MEM (0x5000_0000) is greater than the calculated size of the BAR4 (0x40000000). This parameter is not configurable from the the Qsys GUI interface. The reference design documentation says it is automatically calculated when I finish the interconnection. 

 

I would like to know if any of you guys have had this problem and what I am doing wrong. I want to be able to write any position on the design using iowrite32 calls. 

 

Thank you a lot for any help you could give me. 

 

Amorim
0 Kudos
0 Replies
Reply