I am targeting Arria 10 GX 570 FPGA for custom protocol development using Transceivers.
I am using Bank 1C primarily for PCie x2 (as this bank contains PCIe Hard IP). So PCIe will use channel 4 & channel 5 with the bonded mode.
In the same bank (1C), 4 channels are left [channel 0 to channel 3]. So I want to use those channels DP interface using Intel's DP (displayport) IP which also needs the lane bonding.
So, my concern is whether I can use 1C bank for 2 different protocols which requires Lane bonding requirement ?
As I understand it, you have some inquiries related to the placement of channels within a XCVR bank of A10 device. Just to check with you what is the TX PLL used for the PCIex2? If you are using CMU PLL, you are left with only 3 channels for DP (2 left if you are using CMU PLL).
Regarding the bonding, there should be no issue to have two bonded groups within the same XCVR bank as there are two MCGBs. However, it is recommended for you to create a simple test design and run through Fitter compilation to check against internal placement rules.
Please let me know if there is any concern. Thank you.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.