Arria 10 LVDS Tx 16 channel compile issue

[JWang21]

Hi ,

I would like to implement the LVDS Tx 16 channel on Arria 10 device. (10AX027H4F34I3SG)

But have the error message as below, would you guide me how to resolve the problem?

I also upload the project in the attachment.

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS_CLOCK_TREE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

    Error (175020): The Fitter cannot place logic LVDS_CLOCK_TREE that is part of LVDS SERDES Intel FPGA IP LVDS_TX_SERDES_altera_lvds_191_blkigey in region (84, 5) to (84, 59), to which it is constrained, because there are no valid locations in the region for logic of this type.

        Info (14596): Information about the failing component(s):

            Info (175028): The LVDS_CLOCK_TREE name(s): LVDS_APP:LVDS_APP|LVDS_TX_TOP:LVDS_TX_TOP|LVDS_TX_SERDES:CH_13|LVDS_TX_SERDES_altera_lvds_191_blkigey:lvds_0|LVDS_TX_SERDES_altera_lvds_core20_191_tptsi5q:core|altera_lvds_core20:arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst

        Error (16234): No legal location could be found out of 6 considered location(s).  Reasons why each location could not be used are summarized below:

            Info (175013): The LVDS_CLOCK_TREE is constrained to the region (84, 5) to (84, 59) due to related logic

                Info (175015): The I/O pad USER_CLK is constrained to the location PIN_H19 due to: User Location Constraints (PIN_H19) File: D:/intelFPGA/19.1/Project/AMTC3_FPGA_TOP/Verilog Code/AMTC3_FPGA_TOP.v Line: 111

                Info (14709): The constrained I/O pad drives a IOPLL, which drives this LVDS_CLOCK_TREE

            Error (175006): Could not find path between the LVDS_CLOCK_TREE and destination LVDS_CHANNEL

                Info (175027): Destination: LVDS_CHANNEL LVDS_APP:LVDS_APP|LVDS_TX_TOP:LVDS_TX_TOP|LVDS_TX_SERDES:CH_13|LVDS_TX_SERDES_altera_lvds_191_blkigey:lvds_0|LVDS_TX_SERDES_altera_lvds_core20_191_tptsi5q:core|altera_lvds_core20:arch_inst|channels[0].tx.serdes_dpa_inst~CHANNEL

                    Info (175015): The I/O pad TX_OUT_13[0] is constrained to the location PIN_AE12 due to: User Location Constraints (PIN_AE12) File: D:/intelFPGA/19.1/Project/AMTC3_FPGA_TOP/Verilog Code/AMTC3_FPGA_TOP.v Line: 162

                        Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL

                Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements

                Info (175021): The LVDS_CHANNEL was placed in location LVDS_CHANNEL containing AE12

                Info (175029): 6 locations affected

                    Info (175029): LVDSCLOCKTREE_X84_Y5_N4

                    Info (175029): LVDSCLOCKTREE_X84_Y5_N5

                    Info (175029): LVDSCLOCKTREE_X84_Y32_N4

                    Info (175029): LVDSCLOCKTREE_X84_Y32_N5

                    Info (175029): LVDSCLOCKTREE_X84_Y59_N4

                    Info (175029): LVDSCLOCKTREE_X84_Y59_N5

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

Error (16297): An error has occurred while trying to initialize the plan stage.

Error:

Error: Quartus Prime Fitter was unsuccessful. 8 errors, 2 warnings

    Error: Peak virtual memory: 1984 megabytes

    Error: Processing ended: Tue Aug 11 09:40:50 2020

    Error: Elapsed time: 00:00:22

    Error: Total CPU time (on all processors): 00:00:22

Thanks,

Jay