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Arria 10 Native Transceiver PHY 10GBASE-R w/KR FEC Clocks

FHint
New Contributor I
308 Views

Hello,

I am currently struggling with the Arria 10 Native Transceiver configured with the 10GBASE-R /wKR FEC preset.

I am using the following document as reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr...

In Figure 57 you can see that the tx_clkout and rx_clkout have 161.1 MHz and that the tx_coreclkin and rx_coreclkin are meant to have 156.25 MHz (from XGMII).

Now with the above mentioned preset the tx_pma_div_clkout is configured as 5156.25/33 = 156.25 MHz. The rx_pma_div_clkout is disabled.

My questions are:

1) Is the tx_pma_div_clkout destined to be used for my custom FPGA fabric (MAC, data preprocessing, ...) and the tx_coreclkin?

2) Shall I activate the rx_pma_div_clkout to do the same here? If so, why is it not activated by default?

3) If the answers to 1) and 2) are yes, what is the purpose of the tx_clkout and rx_clkout?

A similar question has already been asked here but unfortunately it wasn't answered.
https://community.intel.com/t5/Programmable-Devices/Arria-10-Native-Transceiver-PHY-10GBASE-R/m-p/16...

Thank you in advance!

Best Regards

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1 Solution
CheePin_C_Intel
Employee
291 Views

Hi,


As I understand it, you have some inquiries related to the A10 Native PHY in 10GBaseR mode. Please see my responses as following:


1) Is the tx_pma_div_clkout destined to be used for my custom FPGA

fabric (MAC, data preprocessing, ...) and the tx_coreclkin?

[CP] Yes, your understanding is correct. This clock is of 156.25MHz which is to use with the XGMII interface and connect to xgmii_tx_clk/xgmii_rx_clk


2) Shall I activate the rx_pma_div_clkout to do the same here? If so,

why is it not activated by default?

[CP] You can use tx_pma_div_clkout for xgmii_tx/rx_clk. So, this clock is not used by default.


3) If the answers to 1) and 2) are yes, what is the purpose of the

tx_clkout and rx_clkout?

[CP] These are clocks used to clock in the internal blocks of the XCVR channels.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


View solution in original post

4 Replies
CheePin_C_Intel
Employee
292 Views

Hi,


As I understand it, you have some inquiries related to the A10 Native PHY in 10GBaseR mode. Please see my responses as following:


1) Is the tx_pma_div_clkout destined to be used for my custom FPGA

fabric (MAC, data preprocessing, ...) and the tx_coreclkin?

[CP] Yes, your understanding is correct. This clock is of 156.25MHz which is to use with the XGMII interface and connect to xgmii_tx_clk/xgmii_rx_clk


2) Shall I activate the rx_pma_div_clkout to do the same here? If so,

why is it not activated by default?

[CP] You can use tx_pma_div_clkout for xgmii_tx/rx_clk. So, this clock is not used by default.


3) If the answers to 1) and 2) are yes, what is the purpose of the

tx_clkout and rx_clkout?

[CP] These are clocks used to clock in the internal blocks of the XCVR channels.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


View solution in original post

FHint
New Contributor I
284 Views

Hi,

thank you a lot for the answer! Then I'll just use the tx_pma_div_clkout for the XGMII interface and the tx_coreclkin/ rx_coreclkin.

Regarding question number 3 and just for my better understanding: Is there any purpose to the 161 MHz tx_clkout and rx_clkout outside of the Transceiver PHY?

Best Regards
Florian

CheePin_C_Intel
Employee
274 Views

Hi,


Regarding the latest inquiry on the tx/rx_clkout, I am not sure about the specific usage for user in core since I am not really a design specialist. Sorry for the inconvenience.


CheePin_C_Intel
Employee
249 Views

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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