FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6020 Discussions

Arria 10 PCIe Hard IP Automatic Lane Polarity Inversion



I am considering using Arria 10 but there is one thing I'd like someone to throw some light on. I checked  Arria 10 devices errata  and I found the following:

[For Intel Arria 10 PCIe Hard IP open systems where you do not control both ends of
the PCIe link, Intel does not guarantee automatic lane polarity inversion with the
Gen1x1 configuration, Configuration via Protocol (CvP), or Autonomous Hard IP mode.]

Because of the data transfer speed needed I am planning on using PCIe gen3 x8. Obviously in order to meet the PCIe 100ms time I either have to implement Cvp or Autonomous configuration mode, but in this case there is a probability that the automatic lane polarity inversion feature may not work correctly causing the PCIe link training to fail.  

I would like some advice on whether or not there is a workaround this.

I've read about the "RX-polarity inversion in soft logic" feature but again It does not support neither CvP nor autonomous mode.

What are the probabilities of this problem to occur? as there is little info about it I think that are low.

any comments welcome.

Best Regards.

0 Kudos
2 Replies

I gone through the Errata and the details, from the below , I assume you are planning to use PCIe gen3 x8, in that case, the below Errata does not apply ,

 And I am curious why you have to use CVP ,is there any particular reason ( only need to  achieve  PCIe 100ms time ) 

The above question is to understand the issue more  

Or are you expecting me to provide the worst case analysis? on a perticular scenario



Hello Rhaul 

Thank you for your reply. I will answer to your question below.

That is right, my board is PCIe gen3 x8. 

I am not using CvP, instead I am using Autonomous mode in order to meet the PCIe 100ms time.

 I read the Errata and it looks like PCIe gen x8 is actually affected too when using Autonomous Mode (link below page 6).

If it is not affected, would you provide some documentation on this please? As I stated,  I do not control both ends of the PCIe.