Arria 10 Receiver-Transceiver PHY calibration

[TerryU]

Hi experts,

I use Arria 10 device and configure SAS (Serial Attached SCSI) interface. When I assembled many boards, and then around 10% boards failed with SAS link error.

In my analysis on Signal TAP, receiver was not locked.

In SAS initial link stage, now I use 6Gbps rate, the rate migrates from 3Gbps to 6Gbps. And the receiver was not locked the first 3Gbps.

It is described that it shall do re-calibration at the rate change. However it would be not described calibration function details.

What is the actual function of calibration and how does it effect to receiver-phy? I guess that it would effect to PLL optimization. Is it correct?

Thanks,

TerryU

[CheePin_C_Intel]

Hi TerryU,

As I understand it, you have some inquiries related to A10 XCVR RX calibration.

Specific to your inquiry of "What is the actual function of calibration and how does it effect to receiver-phy? I guess that it would effect to PLL optimization. Is it correct?", for your information, after you perform a rate change to the XCVR, a recalibration is required to fine tune the internal parameters of the TX PLL, RX PMA and TX PMA to ensure that they are optimal at your new data rates. This is also to ensure that XCVR blocks will operate as expected at the new data rates. You may refer to the A10 XCVR PHY user guide -> "Figure 284. Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes" for the blocks that required to be recalibrated after a rate change.

Just would like to check with you when you switch to 3Gbps and perform user recalibration, the RX CDR still unable to achieve lock to data? Or unable to achieve lock to reference as well?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[xytech]

Hi Chee, @cheepinc_Intel​ 

Your answer helps. Recently I am really struggling with this Calibration thing. From your words, "recalibration is required to fine tune the internal parameters of the TX PLL, RX PMA and TX PMA to ensure that they are optimal at your new data rates. This is also to ensure that XCVR blocks will operate as expected at the new data rates", can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?

If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.

https://forums.intel.com/s/question/0D50P00004Gf0dgSAB/what-would-happen-if-transceiver-calibration-fails

Thanks, and happy weekend.

[TerryU]

Hi Chee,

Thank you for your reply.

Indeed, recalibration would be necessary. And I have found another register "Rate Switch Flag Register", that manages charge-pump​ setting for CDR. I think, it might effect Rx-PLL also. I will do some further inquire and trial.

Thanks.

TerryU

[CheePin_C_Intel]

Hi TerryU, Yes you are right. If you are performing rate change involving CDR, you would need to set the rate switch register following the user guide. Thank you. Best regards, Chee Pin