Arria 10 XVCR oversampling 155Mbps CDR setting

[PTan9]

Dears,

I want to know oversampling 155Mbps CDR setting of Arria 10 XVCR is manual LTR mode? Thanks.

Best Regards

Penn Tan

[Deshi_Intel]

HI Penn Tan,

There is no relationship between oversampling and CDR mode.

You can use either CDR automatic mode or manual mode.

Thanks.

Regards,

dlim

[PTan9]

Hi Dlim,

Custome have used CDR automatic mode to lock to data and used the recovery clock to process the received data according to SDH protocol. But the Loss of LTD signal often occurs because of the long list of zero on receiver.

After the long zero appear on receiver pin, the pcs parallel rx data is wrong data and then CDR has changed from LTD to LTR mode. After the normal data jump appear on receiver pin, the CDR has changed from LTR to LTD mode and then the pcs parallel rx data receive normal data.

​Between the period of long zero appear on receive chain, customer could not get correct data on PCS parallel_rx_data, please suggest how to deal with this problem? Thanks.

Best Regards

Penn Tan

[Deshi_Intel]

Hi Penn Tan,

Yes, CDR will loose lock if encounter long length of zero or one data transfer. This is expected behaviour.

As a workaround,

1. Option 1 - you can use CDR manual mode LTR instead of LTD.
2. Option 2 - I am not sure about SDH protocol but Ethernet protocol utilize 8b/10b encoder/decoder in PCS block to address this kind of issue. 8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.
3. Option 3 - customer needs to manage his/her data transfer to avoid long length of zero or one

Thanks.

Regards,

dlim

[PTan9]

Hi Dlim,

1.Option 1 - you can use CDR manual mode LTR instead of LTD.

Customer have try CDR manual mode LTR, when long length of zero appear on RX PMA, the parallel_rx_data port appear error data.

2.Option 2 - I am not sure about SDH protocol but Ethernet protocol utilize 8b/10b encoder/decoder in PCS block to address this kind of issue. 8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.

155Mbps serial data stream have been scrambled for DC balance and limits the maximum number of consecutive 1s and 0s in the serial data stream from SDH network equipment, so the RX PCS 8B/10B have been disable. Customer will manually do descrambler of receiver data from parallel_rx_data port using used the recovery clock. There must be a long length of zero that are detected on RX PMA because of 10X oversampling(Serial rate is 1.25Gbps), so we want to know how to receive correct data and LTD will not change to LTR with CDR automatic mode when detected a long length of zero on RX?

3.Option 3 - customer needs to manage his/her data transfer to avoid long length of zero or one

​Customer could not manage his/her data transfer to avoid long length of zero or one because the serial data from SDH network.

Best Regards

Penn

[Deshi_Intel]

Hi Penn,

I have consulted internal team further on oversampling operation.

Below is the design guideline.

• Oversampling support can be achieved using CDR LTR manual mode + additional soft CDR logic design
• CDR must not be set to LTD mode in low data rate mode (<1Gbps) as it may loose lock due to nature architecture design to serve higher data rate transmission only
• However the issue with using LTR mode is it's not really generating real recover clock from incoming Rx data anymore hence the data phase maybe difference. Additional soft CDR logic design is required to take care of this issue. I believe your customer design is lacking of this soft CDR logic
• Attached is one of the oversampling reference design design that you can share with customer as reference

Thanks.

Regards,

dlim

[PTan9]

Hi Dlim,

What position do additional soft CDR logic design should been added? before PMA CDR? or use soft CDR parallel to PAM CDR to acquire recover clock from incoming Rx data? Could we acquire incoming Rx data at Transceiver RX pin to soft CDR? Thanks.

Best Regards

Penn

[Deshi_Intel]

Hi Penn,

The soft CDR should be implemented after PMA CDR as it's soft logic design. It's impossible for user can't add any design on the hard circuit transceiver channel.

Rx data is expected to pass through PMA CDR -> soft CDR but I didn't look into the reference design detail implementation as well.

If you unzip the reference design, then you will find reference design.qar and also doc explaining on the design with design owner contact. Feel free to contact the Europe FAE directly which is also the design owner if you wish to understand more on the design.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI Penn,

I hope my earlier feedback is helpful to you.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim