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Honored Contributor I
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Arria 2 DDR3 shared PLL

Hi, 

 

I have two DDR3 instantiations in my design. 

I'm low on PLL resources and I need to share the PLL of the two DDR3 inst. 

In the documentation I saw that the ALTMEMPHY does not support using a shared PLL, and the UNIPHY does. 

I can't seem to use the UNIPHY for the Arria 2 GX although it is stated that it is supported. 

Is it possible to share a PLL for two DDR3 instantiations in Arria 2 GX device ? 

 

Thank You!
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Honored Contributor I
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Is it the PLL you're low on or clock outputs? I'm pretty sure a number of the clocks can be shared via assignments. The altmemphy handbook talks about it. But you're right that altmemphy requires two different PLLs for some of the clcoks.

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Honored Contributor I
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I'm short on PLL's, I have an IP that uses 2 PLL's and is strict and can not be modified. 

2 DDR3 take 1 PLL each. 

And I have 16 channel of LVDS that can be used with external PLL. 

 

Maybe there is a way to feed the LVDS with the DDR3 PLL outputs ?  

 

(LVDS PLL requires an lvds input clock)
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Honored Contributor I
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16 transmit or receive channels? At what data rate? The dedicated True LVDS silicon requires a PLL on that side(as there is a dedicated, low skew low jitter clock tree from the PLL to the SERDES). This generally doesn't combine with DDR3 since they use a top/bottom PLL. That being said, many applications don't need "True LVDS" and work fine with just a PLL. If you're pushing the limits, say 1GB data rates, you need True LVDS, but otherwise might be all right with the LVDS I/O standard, the I/O's double-data rate registers, and a global clock(driven from a PLL elsewhere in the chip).

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Honored Contributor I
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16 transmit and receive. 

The data rate is 500Mbps, it will be implemented using soft LVDS, 

There is no problem to use 1 external PLL for the LVDS tranceivers. 

The problem occures when I have no free PLL's at all. 

Can I derive the LVDS clock inputs from a DDR3 ALTMEMPHY PLL, or is it simply impossible ?
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Honored Contributor I
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Just to clarify, for the LVDS receive data you're also getting a clock, so that clock would need to drive the PLL. I'm not sure. The PLL operation is pretty independent of the input clock's I/O standard, i.e. if you drove it with LVDS and all the frequencies necessary for DDR3 are available, it should work.  

How many PLLs in the device you're using? I take it two are used for altmemphy, but wondering what others are used for(if they exist).
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Honored Contributor I
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I have 4 PLL's, I'm using a closed IP which utilzes 2 PLL's. 

I think there is no option to do what i'm trying. 

Maybe there is something I dont know.
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