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Altera_Forum
Honored Contributor I
834 Views

Arria II GX refclk pins

Hi there, 

 

Is there any assignment I need to set when I use the refclk pins as clk inputs? I am using EP2AGX65CU17C6 device. We connected a differential clock input to pin M19 and M20, which is the refclk[0] pin according to the pinout for this device. But the Quartus gives the following fitting error: 

 

Error: Differential I/O input pin ref_clk_left is assigned to a non differential location M19. However, it must be assigned to a differential input location 

 

Why does Quartus II consider the M19 as a non differential pin? 

 

Thanks, 

Hua
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9 Replies
Altera_Forum
Honored Contributor I
32 Views

You may need to set the clk pins as lvds in the assignment editor. Because the default may be single ended.

Altera_Forum
Honored Contributor I
32 Views

I did set the I/O signal as lvds in pin planner. Is that enough? Are you saying I should set pins M19 and M20 as lvds in the assignment editor?

Altera_Forum
Honored Contributor I
32 Views

Well we are talking about clk pins (not user io). They have to be set as lvds by somebody. Physically you have connected the lvds pair, but it is not clear what you have done in HDL interface itself when declaring the clk. There is some tool inconsistency here. depending on your tool I believe you should try and declare only the positive signal in your entity, you may then get false warning about the negative pin but ignore it.

Altera_Forum
Honored Contributor I
32 Views

In top level entity I declared the input signal like: 

 

ref_clk_left : in std_logic; 

 

Then in pin planner, as the attached screenshot, I assigned the ref_clk_left signal to pin M19, and set the IO standard as LVDS. 

 

I also tried using chip_pin and altera_attribute to do it, but got the same result. 

 

attribute chip_pin: string; -- Altera specific pin assignment constraint 

attribute chip_pin of ref_clk_left : signal is "M19"; 

 

attribute altera_attribute: string; 

attribute altera_attribute of ref_clk_left : signal is "-name IO_STANDARD LVDS"; 

 

What did you mean when you are saying clk pins and user io? are you saying M19 and M20 are clk pins, and ref_clk_left is the user io? If that's the case, how do I set the M19 and M20 pins to be LVDS? 

 

Thanks, 

Hua
Altera_Forum
Honored Contributor I
32 Views

Setting the refclk_p in pin planner should be sufficient, as with any other differential clock or user IO pin. I wonder if LVDS is correct for refclk or if it should use PCML standard.

Altera_Forum
Honored Contributor I
32 Views

Just tried 1.5-V PCML, got the following error msg: 

 

Error: I/O standard "1.5-V PCML" is not valid for I/O pad "ref_clk_left". Only pins connected to GXB transceiver blocks can use this standard.
Altera_Forum
Honored Contributor I
32 Views

Could it be that the ref_clk_left is never used in the design?

Altera_Forum
Honored Contributor I
32 Views

Hua, 

 

This pin clock is for transceivers. It can't be used with other logic. 

 

I'm using EP2AGX65CU17C6N too. I use this pin clock with a PCI Express core (Reference clock from motherboard).  

 

The block of assignment in Quartus Setting File of my project: 

 

set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk 

set_instance_assignment -name INPUT_TERMINATION OFF -to pcie_refclk 

set_location_assignment PIN_M19 -to pcie_refclk
Altera_Forum
Honored Contributor I
32 Views

I removed the the signal from my top level since I am not using it anywhere in the design, then the problem went away. This leads me to think that, if I am driving the ref_clk of the altgxb ip from an internal PLL, I shouldn't be assigning any signal to the dedicated ref_clk pin. 

 

Thank you all for your replies!