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Arria V DDR3-HMC with UniPHY

Altera_Forum
Honored Contributor II
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Hi, 

 

I got some problems with the DDR3-Controller and after spending some days to find a solution i hope you can show me what im doing wrong. 

To figure out my problem, I used one of the starterkit examples for the ddr3-controller and build the smallest possible design and.... it wont work. When I deassert the DDR3-Controller I can open the System-Console and see the JTAG Master and can do read and write operations to the slaves. When the DDR3-Controller is asserted in QSys, I cant even see the JTAG Master in the System-Console. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9758&stc=1  

http://www.alteraforum.com/forum/attachment.php?attachmentid=9759&stc=1  

 

Following the Altera QSys Design example, i found this diagram http://www.altera.com/support/examples/images/qsys_diagram_memory_tester_system.jpg and tried to build it that way, also without success. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9760&stc=1  

 

System-Console cant find any Master with the Command : get_service_paths
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