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Altera_Forum
Honored Contributor I
1,093 Views

Arria V Hard IP for PCI Express Root-point issue

Hi everyone, 

 

I am using Arria V FPGA as pcie root port to connect a Gb Ethernet controller ASIC which used as a pcie endpoint, the diffcult is how to control the pcie root port, there are two ways: 

1.Use a NIOSII CPU to control the pcie root port.  

2.Use application logic to send requester to endpoint and handle the requester from the endpoint 

 

Can anyone tell me which one is the better and the detailed process for these two ways? 

 

 

 

Thanks 

 

Regdrs
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3 Replies
Altera_Forum
Honored Contributor I
33 Views

Is this a board, you are designing now, or is it already done? 

 

The third option is to use the SOC variation of the Cyclone V, and use one of the ARM cpu's to control the PCIe. 

 

Out of the three, this is probably the quickest to get up and running, and the simplest for your software engineers to understand (ARM CPU's are well understood). 

 

NIOS would be my second choice, in most case. Both both the ARM and NIOS subsystems you need to get familiar with QSYS and build your SOC up via that program. 

 

You can use logic to do the sending/requesting, but unless you need absolute minimum overhead/latency in your system, this is much more difficult to implement. 

 

Take a look at the SOC's I've used the Cyclone V variation, and Zynq variation (Xilinx) and have been impressed. Altera's QSYS is a better tool for connecting the components and IP. 

 

The number of LE's available in the SOC's are less, but remember, you will not be using ANY LE's or memory blocks for the processor blocks. (Hardcores), where to get a high performance NIOS, will take significant resources. 

 

Regards 

 

Pete
Altera_Forum
Honored Contributor I
33 Views

Tks Pete. Our board are designing now, But we need Arria V in our system. 

Now our VP decide to use logic to do the sending/requesting.
Altera_Forum
Honored Contributor I
33 Views

No problem. 

 

If the boards are in the design phase now, there is an Arria V soc as well. (I don't know if it's release yet or not). 

 

The thing to do is look at the pinout requirements between the SOC and the Non-SOC variants. Although Altera is not stating pin compatibility between the two families, you may find you can make it work. (I found it was possible with Cyclone V, but there were limitations) 

 

At the vary least, you should find all the Arria V members in that package, and make sure you don't use pins that would make it impossible to go up/down family members in the same package. Often some pins are NC or defined as extra VCC/GND depending on the family member. (Typically larger part needs more VCC/GND pairs and smaller parts may not have all the IO) 

 

Best of luck in your design. 

 

Pete
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