FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Arria V PCIe Hard IP sees stale data

Honored Contributor II

Can anyone explain this failure ... I am looking on the X1 link but need to verify if the write data in the FPGA went to the correct IMEM location. 


Looks like the write data is returned after the third read. 


Reloading the FPGA appears to correct the issue ....  


Thanks in Advance
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