FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Arria V PCIe hard IP

Honored Contributor II

Hello everbody, I need help about PCIe configuration. 

I work with arria V and i use PCIe hard IP. 

My question is , we can have PCIe soft IP in Arria V ? 


and my last question is we can drive in FPGA the input signal pin_perst of PCIe ? 


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3 Replies
Honored Contributor II

What is your reason for going to soft IP?

Honored Contributor II

Because in the final card of my project i have affected the wrong signal for the reset pine and the final card is already been manufactured. 

So i have to move the reset pine in the arria 5 but it is impossible because this pin is dedicated pine. 

I thought if i use SOFT core i can chose the all pine who will use the PCIe. 


sorry my english is not very good , i don't know if you understand. 


thanks for your time.
Honored Contributor II

For Arria V device, the mapping of nPERST is as below: 

- nPERSTL0 --> bottom Hard IP of pin_perst 

- nPERSTL1 --> top Hard IP of pin_perst 


In your case, try workaround it by changing to use Soft Reset Controller. 

Using Soft Reset Controller doesn't required the connection to pin nPERSTL0. Tie pin_perst to 1 at top level file and nPERSTL0 can be left unconnected at pin assignment. 


Steps to switch to soft reset controller in Qsys: 

1) Edit the .qsys file 

2) Search for the string 'force_src' 

3) Set parameter force_src to 1: 

<parameter name="force_hrc" value=0" /> 

<parameter name="force_src" value=1" /> 

4) Save the changes to the .qsys file and regenerate the Qsys system. 

5) Use npor input to reset the core and application logic.