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Arria V Starter Kit: SDI re-transmitter

Altera_Forum
Honored Contributor II
781 Views

Hi, 

 

Using Arria V Starter Kit I'm trying following: 

 

  1. Apply HD video to SDI input;  

  2. Inside the FPGA: Receive HD video using standard SDI 14.0 IP module in RX mode;  

  3. Inside the FPGA: Transfer it to another standard SDI 14.0 IP module in TX mode;  

  4. Output the SDI re-encoded video from SDI output.  

 

 

 

RX side separately works properly as well as the TX side. 

 

The problem starts when I connect all together. The SDI RX decodes video with its own pixel clock based on its ref. clock. The SDI encoder produces its own pixel clock based on another ref. clock.  

 

Thus I have two separate clock domains: one for RX side, another for TX side. The frequency is similar but not actually same, then any FIFO buffer I use for clock domains crossing overflows or underflows after some period of time.  

 

Of course, I may build QSYS-based video processor including Video Frame Buffer in triple buffer mode.  

It will work, however I need some much more simple solution. Is it existing? 

 

Thanks
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1 Reply
Altera_Forum
Honored Contributor II
68 Views

Ok. 

I have found the solution by myself. 

I provide it here, may be it will be useful for somebody. 

The SDI TX reference clock input has to be connected to SDI RX restored clock output through a standard Atera's PLL in direct mode w/o frequency conversion . Altera claims that from jitter minimization point of view it is not the best solution (Table2-1, https://www.altera.com/en_us/pdfs/literature/hb/arria-v/av_53001.pdf). However both SDI analyzers show proper eye opening with relatively low jitter about 0.1 UI. 

Regards.
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