Hi,Using Arria V Starter Kit I'm trying following:
Ok.I have found the solution by myself. I provide it here, may be it will be useful for somebody. The SDI TX reference clock input has to be connected to SDI RX restored clock output through a standard Atera's PLL in direct mode w/o frequency conversion . Altera claims that from jitter minimization point of view it is not the best solution (Table2-1, https://www.altera.com/en_us/pdfs/literature/hb/arria-v/av_53001.pdf). However both SDI analyzers show proper eye opening with relatively low jitter about 0.1 UI. Regards.