Arria V from TSE to 2.5G

[host]

A system is currently using an Arria V with the Triple Speed Ethernet IP in PCS only configuration. The design is successfully communicating with other SGMII capable devices at 10/100/1000 speeds.  

A requirement arose to add 2.5G SGMII support on the same device maintaining backwards compatibility with the lower 10/100/1000 speeds we already support.

What Intel IP can support that ?

[paveetirrasrie_Intel]

Hello,

Good day to you.

You may consider V-Series Transceiver PHY IP :

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/about-the-1g-2-5g-5g-10g-multi-rate.html

Regards,

Pavee

[host]

Thanks for your input.

The FPGA in question is an Arria V: 5AGXBA5D6F35C6

1. Will this IP work on any GBx transceivers the device has ?

2. What about lower speeds ? Can the IP you suggested support  10/100/1000 as well as 2.5G ?

[paveetirrasrie_Intel]

Yes it can be done but we have not validated it.

What I would suggest is if you want to support both backplane 2.5G and standard 10/100/1000M, you may use TSE IP for SGMII interface and use transceiver PHY IP for 2.5G SGMII/1000Base-X and add control logic to switch interfaces based on detected link type.

Regards,

Pavee

[host]

Regarding your suggesting of "add control logic to switch interfaces based on detected link type"

How do you suggest to do that ?

From what I see, the IP populates the fabric up to and including the transceiver pin.

Are you suggesting to add some kind of high speed transceiver MUX between the 2.5G and 10/100./1000M IPs  and the FPGA transceiver pin ?

[paveetirrasrie_Intel]

Hello,

Good day to you.

Yes, you may need control logics to identify which interface is active, MAC selection MUX which routes TX/RX data based on control logic but need to ensure only one MAC path is active at a time.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

Good day to you.

Kindly let me know if my previous suggestion helps.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

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Thank you.