Arria10 EMIF Design Example Simulation

[LSant1]

I generated the design example for Arria10 EMIF. I tried to simulate it following the instructions in the example design user guide. But I get all blank waveforms. Is there any step missing? Am I required to create my own testbench?

Lakshmi

[Vicky1]

Hi Lakshmi,

"But I get all blank waveforms. Is there any step missing? Am I required to create my own testbench?"

No need to write testbench since simulation script is already generated.

What do you mean blank waveforms?

Have you done " Add Wave" step?

Try once again with each & every step carefully.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[LSant1]

Yes, I did that. I only see the clock running. I tried to force the reset and that did not help.

Lakshmi

[Vicky1]

Hi Lakshmi,

Try once again with each & every step carefully.

try to run for "run 100" & check.

"What do you mean blank waveforms?" please provide screen shot.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[LSant1]

I used the example design and created simulation script using "Generate test bench system" which had the simulation model setting. In modelsim, I ran source msim_setup.tcl and then ld_debug. Attached is the waveform output.

[LSant1]

I tried it all over again and this time I did not choose Modelsim simulator as the EDA tool in Quartus. I regenerated the IP core files, compiled the project in Quartus. Then I ran msim_setup.tcl and ld_debug. The simulation goes on for a very long time and the waveform still looks as shown in the attachment in the previous message. I used Arria10 SoC Dev Kit DDR4 HILO(x72) preset and used all the default settings.

[Vicky1]

Hi Lakshmi,

"Yes, I did that. I only see the clock running. I tried to force the reset and that did not help."

You can force the signals refer the attachment & then run.

First you need to understand the working of EMIF & then you can perform simulation by forcing appropriate signal.

you can also do one thing ,

1. Perform "Start Analysis & Synthesis" then
2. Processing -> Start -> Start Test Bench Template writer

It will create .vt file Test Bench File under /simulation/modelsim/arria.vt

for simulation, here provide stimulus & that you can use in NativeLink setting

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[LSant1]

Native link setting seems to be a thing of the past. Its not relevant to Quartus v18.0. I tried providing stimulus for global reset and pll clock. But that's not being enough. Do I need to create a full stimulus? It appears like we don't need to for example designs.

[Vicky1]

Hi,

"First you need to understand the working of EMIF & then you can perform simulation by forcing appropriate signal."

provide the stimulus for important signals & verify them with simulation. If you understand enough EMIF then provide full input stimulus.

For better support further, please open new thread.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[LSant1]

You seem to be talking about older versions of Quartus. I was able to finally run a simulation for a different preset yesterday. There is some problem with the preset for Arria10 SoC devkit DDR4 HILO (x72) example design which is why its not working. For the newer Quartus version, I just need to create the simulation script. In Modelsim, I just need to run

source msim_setup.tcl

ld_debug

The example design includes testbench and stimulus. Please see UG-20115 and UG-20118.

[LSant1]

I was able to simulate the DDR4 preset for Intel board too. This preset does not put out anything in the transcript window for a long time. That made it look like it wasn’t working. Looking at the DDR3 simulation gave me idea about the time I should expect to see the read write transactions. So I let the ddr4 simulation run upto that point and then I started seeing the RW transactions. Again, I did not have to create any stimulus. Its built-in the example design.