We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board.
The design is found to be working in simulation, but on the board, the link doesn't come up. The PCIe LTSSM state is stuck at 0, looks like receiver detection is not happening. The core_clock o/p from the PCIe core looks fine.
We are suspecting PCIe serial link connectivity issue. As per the board document, we could see 10 transceiver channels being connected to the Hard IP. Any idea, which transceiver to be used for Gen1 x1 purpose? Any other pointers to debug this would be of great help.
For PCIe hard IP testing, this is suggested to use the A10 FPGA development kit, where there is a PCIe interface for you to connect to the Root Port.
Here is the link:
As per the SI dev kit, the PCIe group are located at block E & F. See Page 42:
As per the A10 PCIe user guide, the channel 0 of PCIe is starting from channel 4. See figure 21.
Therefore, the PCIex1 should be located at:
I don't aware if there is any for A10. The things that you can do is to capture the signal tap for the LTSSM and see the status, or you can create a simple design by using Native PHY, and then use the Transceiver Tool Kit to analyze the link.
You may start with some simple design which using Native PHY and TTK to perform some loopback test, and ensure your hardware setup is alright.
Yes, the soft PCIe IP can work with native PHY.
For the TTK for transceiver link, you may refer the link below as starting point.
To confirm your design is working fine for the external loopback, you can change the pin assignment to the channel that using 2.4 SMA connectors. If this passed, then you need to double check on your hardware setup. And maybe using a scope to confirm if there is a signal sending out from TX.