Arria10 PCIe Hard IP link bring up issue

[SKuma36]

Hi,

We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board.

The design is found to be working in simulation, but on the board, the link doesn't come up. The PCIe LTSSM state is stuck at 0, looks like receiver detection is not happening. The core_clock o/p from the PCIe core looks fine.

We are suspecting PCIe serial link connectivity issue. As per the board document, we could see 10 transceiver channels being connected to the Hard IP. Any idea, which transceiver to be used for Gen1 x1 purpose? Any other pointers to debug this would be of great help.

rgds,

sunil

[SengKok_L_Intel]

​Hi Sir,

For PCIe hard IP testing, this is suggested to use the A10 FPGA development kit, where there is a PCIe interface for you to connect to the Root Port. 

Here is the link:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html

Regards -SK

[SKuma36]

Hello SK, Thanks for the response. We don’t have the Arria10 FPGA development kit. We have only the Arria10 Signal Integrity development board. This board also supports PCIe interface via the Samtec Bulls eye connector on the board. We are using one external breakout board to finally connect the SMA signals from the Bulls eye connector to the PCIe edge. Could you pl. help us in understanding the transceiver channels used for this PCIe Hard IP block? We would like to know what FPGA pins to be used to connect the PCIe serial interface signals. If you have any document on this, pl. share it with us. Rgds, sunil

[SengKok_L_Intel]

Hi Sunil,

As per the SI dev kit, the PCIe group are located at block E & F. See Page 42:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_si_dev_kit.pdf

As per the A10 PCIe user guide, the channel 0 of PCIe is starting from channel 4. See figure 21.  

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

 Therefore, the PCIex1 should be located at:

GXBR_4E_TX_4n

GXBR_4E_RX_4n

Regards -SK

[SKuma36]

Hi SK, Thanks for the info. Is it possible to change the location of channel 0 of PCIe to some other channel other than channel 4 (Block E) ? I tried using channel 0 (Block F), but Fitter operation resulted in error. Pl. check the attached snapshots. Rgds, sunil

[SengKok_L_Intel]

​Hi Sunil,

No, this is not possible. The location of hard IP is fixed, and you have to follow.

Regards -SK

[SKuma36]

Hi SK, Ok got it. Is there any way we can debug this link bring up issue? I could see some PCIe Link Inspector tool for Stratix 10 FPGA. Do we have any such thing for Arria 10 FPGA? Rgds, sunil

[SengKok_L_Intel]

​Hi Sunil,

I don't aware if there is any for A10. The things that you can do is to capture the signal tap for the LTSSM and see the status, or you can create a simple design by using Native PHY, and then use the Transceiver Tool Kit to analyze the link.  

Regards -SK

[SKuma36]

Hi SK, I tried capturing the PCIe LTSSM state with SignalTap (snapshot attached). The state machine transitions between Detect_quiet (00) and Detect_Active (01) states, doesn’t goes to Polling state. Looks like receiver detection has failed. I tried looping back TX & RX lines, still see the same issue. Also tried probing the internal PIPE signals, but no activity is seen. Pl. suggest if I need to probe any other signals. Rgds, sunil

[SengKok_L_Intel]

​Hi Sunil,

You may start with some simple design which using Native PHY and TTK to perform some loopback test, and ensure your hardware setup is alright.

Regards -SK

[SKuma36]

Hi SK, Is it possible to use a soft PCIe IP core instead of Hard IP for Arria10 FPGA? Rgds, sunil

[SengKok_L_Intel]

​Hi Sunil,

Yes, this is possible if you have your own soft PCIe IP or from third party.  

Regards -SK

[SKuma36]

Hi SK, Even if we have our own soft PCIe IP core, we should still use Arria10 Native Transceiver PHY, right? In that case, can we configure the transceiver for PCIe protocol? Rgds, sunil

[SKuma36]

Hi SK, As suggested by you in an earlier email, I thought of using the TTK for Transceiver link debugging. Do we have any example designs that we can use for this? If so, could you pl. share the link for the same? Pl. note that we are using Arria 10 Signal Integrity development board. Rgds, sunil

[SengKok_L_Intel]

​Hi,

Yes, the soft PCIe IP can work with native PHY.

For the TTK for transceiver link, you may refer the link below as starting point.

https://fpgawiki.intel.com/wiki/Arria10_Transceiver_PHY_Basic_Design_Examples#Arria_10_Native_PHY_with_Transceiver_Toolkit_design_example

Regards -SK

[SKuma36]

Hi SK, Thanks for the info. BTW, I tried using the Arria10 SI Board Test system application for testing the transceivers. None of the transceivers connected to Bulls eye connector works in external loopback mode (see attached snapshot). I tried varying the PMA settings, but didn’t see any data looped back from TX to RX side. Any idea what could be causing this issue? The internal serial loopback mode test works fine though. FYI, the transceivers connected to the 2.4 SMA connectors on the board worked fine in external loopback mode when tested with the Board test system application. Rgds, sunil

[SengKok_L_Intel]

​Hi Sir,

To confirm your design is working fine for the external loopback, you can change the pin assignment to the channel that using 2.4 SMA connectors. If this passed, then you need to double check on your hardware setup. And maybe using a scope to confirm if there is a signal sending out from TX.

Regards -SK

[SKuma36]

Hi SK, Our design works fine for the external loopback with the channel connected to 2.4 SMA connector. For the channel connected to High Density bulls eye connector, it’s not working. As suggested, we will try to use a scope and see if we could see data on TX lines. Rgds, sunil