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Arria10 PCIe need two DMAs, (one for data moving ; the other for control msg transfer)

JET60200
New Contributor I
498 Views

Hi expert:

 

Now we use Arria10 w/ PCIe Gen3x8(AVMM-DMA IP setting), which means we have avmm-dma engine for data moving now, and it works well in our product. 

 

But now we  request to add “control message” communication between the Host and the SLave PCIe card (A10).  Can we add another new DMA IP instance  in  FPGA  code, in order to instantiate to support the Control Messsage Transfering between HOst and FPGA?  If yes, how to implement that ? 

 

bty:  we cann't mix to use the same one AVMM-DMA Engine to move both “Pure Data” and the "Control Message”,  thus we need another one DMA engine to do that . 

 

Thanks In advance  

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1 Solution
SengKok_L_Intel
Moderator
440 Views

Hi,


You can refer to the following link chapter 30 for the detail of the MSGDMA:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf


This depends on your application and requirement to customize the arbitrator and descriptor controller. Hence, I might not able to provide further design recommendations.


Regards -SK


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7 Replies
SengKok_L_Intel
Moderator
484 Views

The multiple DMAs setting is NOT supported on Arria 10 PCIe AVMM DMA IP, and there is no similar example available at this moment.


Regards -SK


JET60200
New Contributor I
480 Views

Thanks @SengKok_L_Intel  for reply,

 

  If we consider   “PCIe AVMM IP setting” (instead of AVMM DMA IP ),  is it possible to connect  "two independent mSGDMA instances" to this single “PCIe AVMM IP‘s’" TXA Slave Port ?  

 

What I means is  "  the two sMGDMA module will mainatein their own pcie DMA operation seperately, while share the same gen3x8 PCIE BUS” , Does this implementation  feasible, and does it need an arbitrator ?   Thanks a lot   

SengKok_L_Intel
Moderator
470 Views

Yes, this should be doable with your custom logic with the arbitrator and a descriptor controller that design to handle it.


JET60200
New Contributor I
463 Views

OK,  Thanks @SengKok_L_Intel  for answer & suggestion,

But we have further questions:

 

1)   Where to find " MSGDMA User Guide" ,  also an example design on Arria10 ?   I 'd like to check for evaluation. 

 

2)  regarding of " the arbitrator and a descriptor controller ",  can you clarify more details of " HOW TO IMPLEMENT that " ?  (Is it mandatory for 2 DMA engine to work together ? )

 

Thanks again for expertized answer  

 

 

SengKok_L_Intel
Moderator
441 Views

Hi,


You can refer to the following link chapter 30 for the detail of the MSGDMA:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf


This depends on your application and requirement to customize the arbitrator and descriptor controller. Hence, I might not able to provide further design recommendations.


Regards -SK


JET60200
New Contributor I
428 Views
SengKok_L_Intel
Moderator
364 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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