FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
The Intel sign-in experience is changing in February to support enhanced security controls. If you sign in, click here for more information.
6065 Discussions

Arria10 PCIe: no completion for endpoint MRd

Honored Contributor II

Hello board, 


I am using the Arria10 PCIe HIP (avst) as an endpoint. 


I have PIO read/write working as well as posted writes. I am trying to get non-posted read working, but I have not had much chance so far. 


AFAICT my TLP header looks good, as well as my creds; bus mastering is enabled; but I am not getting neither a completion nor do I see any error reported on the root. 


Here is what I am sending (in hex on a 256b bus): 


00000000 00000000 00000000 00000000 00000000 00117500 050000FF 00000002 


So, in layman terms: 


- length = 2 DWORDS 

- first/last byte enable : 0xFF (all) 

- requested ID : 05:00.00 

- host physical address: 0x117500 


If anyone has any idea what I am doing wrong, any help would be appreciated. 


Thanks !
0 Kudos
2 Replies
Honored Contributor II

After fiddling with the transaction size I realized that 1 DWORD read request work. Anything bigger than 1 DWORD is ignored. I read somewhere that Avalon-MM interface has a single-dword completer mode; however, I am using the Avalon-ST interface so I don't think it applies.

Honored Contributor II

So, as it turned out completion were actually sent. It's just that SignalTap would not catch it as it would happen too soon after the previous breakpoint.