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Arria10 SOC Design Example for 10Gbe with IEEE1588 PTP Capability tested with Quartus Prime Pro

mark_lee
New Contributor I
446 Views

HOW can I get the "Arria10 SOC Design Example for 10Gbe with IEEE1588 PTP Capability tested with Quartus Prime Pro version 19.2。

thanks!

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6 Replies
EBERLAZARE_I_Intel
427 Views

Hi,

We currently do not have the design example for Arria 10 SoC. However, we do have design example for Stratix 10 SoC:

https://rocketboards.org/foswiki/Projects/Stratix10SoCDesignExampleFor10GbeWithIEEE1588PTPCapability

 

 

mark_lee
New Contributor I
413 Views
LarryY
Beginner
331 Views

I'm trying to get PTP working on Arria10 SoC, with the Marvell Alaska ethernet transceiver.

ethtool confirms that it supports hardware timestamps, but getting RX hw timestamp of 0, and ptp4l complains that SYNC doesn't have timestamp.

Some output captured on stdout:

ptp4l[2301.995]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE

[ 2302.290489] socfpga-dwmac ff800000.ethernet eth0: get valid RX hw timestamp 0

ptp4l[2302.260]: port 1: received SYNC without timestamp

[ 2302.313490] socfpga-dwmac ff800000.ethernet eth0: get valid RX hw timestamp 0

[ 2302.812969] socfpga-dwmac ff800000.ethernet eth0: get valid RX hw timestamp 0

ptp4l[2302.783]: timed out while polling for tx timestamp

ptp4l[2302.783]: increasing tx_timestamp_timeout may correct this issue, but it is likely caused by a driver bug

ptp4l[2302.783]: port 1: send delay request failed

ptp4l[2302.783]: port 1: UNCALIBRATED to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED)


Any likely candidates for this error? It's unlikely to be the PTP packets coming in,  as if I use ptp4l in Software timestamp mode, it works. I attached the kernel build .config as config.txt (needed to append .txt so I can upload it). Also note that I am using older code and tools, from Quartus 18.0 Pro.

mark_lee
New Contributor I
319 Views

Hi larryY

    check the clock set  and the ptp is enable

LarryY
Beginner
312 Views

More information from ethtool:

root@socfpga:~# ethtool -T eth0
Time stamping parameters for eth0:
Capabilities:
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
PTP Hardware Clock: 0
Hardware Transmit Timestamp Modes:
off (HWTSTAMP_TX_OFF)
on (HWTSTAMP_TX_ON)
Hardware Receive Filter Modes:
none (HWTSTAMP_FILTER_NONE)
all (HWTSTAMP_FILTER_ALL)
ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT)
ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
root@socfpga:~#


I'm not sure how to check "the clock set"?

mark_lee
New Contributor I
305 Views

Hi LarryY

       The enclosure is "Arria 10 Scalable 10G Ethernet MAC+ Native PHY with IEEE1588v2 Design"。

---FYI

       You can make a new subject , so many more people can help you .

 

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