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Arria10 no "EMIF_USR_CLK" out( DDR4), thus "EMIFDebug KIT" says “Could not accurately determin conne

JET60200
New Contributor I
225 Views

hi all, 

we made a customer Arria10 SX Board, with total 4GB DDR4 on PL side ( using MT40A512M16LY-062E ). THE ddr4ref clock is "133.333MHz", 

we followed "ug-20115 EMIf Arria10 IP User Guide " to generate an EMIF example design,  and the design can be compiled .And sof can generated.

But when programming *sof onto the customer board,  " EMIf Debug Toolkit   " shows below error when trying to Link Project to Device, as :

"

*******************************************************************
Running Quartus Prime Shell
*******************************************************************
The Quartus Prime Shell supports all TCL commands in addition
to Quartus Prime Tcl commands. All unrecognized commands are
assumed to be external and are run using Tcl's "exec"
command.
- Type "exit" to exit.
- Type "help" to view a list of Quartus Prime Tcl packages.
- Type "help <package name>" to view a list of Tcl commands
available for the specified Quartus Prime Tcl package.
- Type "help -tcl" to get an overview on Quartus Prime Tcl usages.
*******************************************************************
load_package ::quartus::external_memif_toolkit
1.0
project_open -force "E:/AlteraFPGA/example/DDR4/example_19_2_pro/ip/emif_0_example_design_2133p_mon/qii/ed_synth.qpf" -revision ed_synth
initialize_connections
Preparing to create a connection to System Console. This may take several seconds.
A connection to System Console was successfully established on port 59971
link_project_to_device -device_name {10AS066H1(.|ES)|10AS066H2|..@2#USB-0} -hardware_name {USB-Blaster on localhost (USB-0)} -sof_file {E:\AlteraFPGA\example\DDR4\example_19_2_pro\ip\emif_0_example_design_2133p_mon\qii\ed_synth.sof},,

...

Could not accurately determine connection type for connection emif_0|emif_0|em_jtag_0|jtag_phy_embedded_in_jtag_master|node|sld_virtual_jtag_component|sld_virtual_jtag_impl_inst|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep as the clock of the connection is inactive.
Could not accurately determine connection type for connection emif_0|emif_0|col_if|colmaster|jtag_phy_embedded_in_jtag_master|node|sld_virtual_jtag_component|sld_virtual_jtag_impl_inst|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep as the clock of the connection is inactive.
Could not accurately determine connection type for connection emif_0|emif_0|col_if|colmaster|jtag_phy_embedded_in_jtag_master|node|sld_virtual_jtag_component|sld_virtual_jtag_impl_inst|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep as the clock of the connection is inactive.

"

 

 I checked the emif design example code, and all these user_clk is comes from "EMIF_USR_CLK" which generated out from the emif controller ip.  I measure the 133.333MHz ref clock is there, so the question is :  why "EMIF_USR_CLK" not generated as expect on thie board ?

 

is there any suggestion to isolate issues ?  Thanks 

0 Kudos
2 Replies
Rashmi1
Employee
217 Views

Hello,


I recommend that you check the following points :-

The DDR IP pll ref clock and the memory output clock to the DDR devices are both running and at the correct frequencies.

The DDR IP global_reset_n signal is high


Try reducing the frequency of the JTAG clock signal and see if this helps. See KDB :

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...


If these points don't help, can you confirm if your project is just the auto-generated example design project generated from the DDR IP or does it contain additional logic from your design ?


Thanks,

Intel Forum Support


JET60200
New Contributor I
207 Views

Thanks @Rashmi1  for suggestion,

 

we rollback to use Quartus Standard 18.1 to generate an EMIF Example Design, and it succeed to run on our A10SOC board.  You can close this ticket. Thanks for help ~

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